Typically a computer chip package in a mid-plane includes a substrate sandwiched between a die, which houses a central processing unit (CPU) or other ASIC chip, and a main logic board, such as a printed circuit board (PCB). Layering the substrate between the die and main logic board allows a manufacturer to use less expensive materials to form the main logic board, thereby saving costs.
The overall thickness of the die/substrate/PCB package is known as the package's “Z dimension,” which refers to the height of the package along the “z-axis” perpendicular to the x-y plane. In a typical arrangement, the die is approximately 0.9 mm in thickness, the substrate is approximately 1.2 mm thick, and the PCB is approximately 1.2 mm in thickness. In addition, at least one ball grid array (BGA) is provided within the package that facilitates coupling and communication between the die and substrate and, in some instances, between the substrate and main logic board. Accordingly, the Z dimension of the package and PCB is typically between about 3.3 mm (LGA) and 4.2 mm (BGA).
As computer devices become smaller and thinner, the need to minimize the Z dimension of the chip package becomes more important. Accordingly, a need exists for an improved mid-plane chip package design and/or arrangement that reduces the Z dimension of the chip package.